The present invention relates to a semiconductor integrated circuit apparatus and more particularly to a floating point adder-subtracter circuit pursuant to the IEEE (Institute of Electrical and Electronics Engineers) standard.
Pursuant to the IEEE 754 standard, a normalized number and a non-normalized number are defined as indicated by formula (1) in connection with data of 32-bit floating point form: EQU normalized number (-1).sup.S 2.sup.E-127 (1.F) EQU non-normalized number (-1).sup.S 2.sup.0-126 (0.F) (1)
where S is a sign value, E is an exponent value before being biased and F is a mantissa value following or below the point, the E being a number larger than 1. The S, E and F are represented by one bit, 8 bits and 23 bits, respectively. It will be appreciated from formula (1) that the exponent value of the non-normalized number is 0 and the bias value of exponent value for the normalized number and that for the non-normalized number are different from each other by 1.
FIG. 3 is a block diagram of a prior art floating point addition-subtraction apparatus. Two operands to be inputted are designated by X and Y, the operand X having a sign part Xs, an exponent part Xe and a mantissa part Xf and the operand Y having a sign part Ys, an exponent part Ye and a mantissa part Yf. A non-normalized number detector circuit 301 receives operand exponent parts (Xe, Ye) to carry out detection as to whether the individual operands are of non-normalized number. A swap circuit 302 is applied with operand mantissa parts (1.Xf or 0.Xf; 1.Yf or 0.Yf) and operable to deliver output signals (data either without or by swapping the inputted operand mantissa parts. A subtracter circuit 303 performs subtraction of the operand exponent parts (Xe, Ye) to deliver an absolute value (.vertline.Xe-Ye.vertline.) and a sign (S(Xe-Ye)). A subtracter 304 subtracts 1 (one) from the absolute value (.vertline.Xe-Ye.vertline.). A right barrel shift circuit 305 is operable to shift an input value supplied from a data line L32, to the right by a desired number of bits the maximum of which is 24 bits. A right shift circuit 306 responds to a signal (indicative of addition) from a shift signal generator circuit 310 to deliver output signals either by right shifting by one digit or without shifting an input value from a data line L31 and an output value (on a data line L33) of the right barrel shift circuit 305.
An adder-subtracter circuit 307 adds or subtracts output values of the right shift circuit 306 to perform a round off processing. A left shift circuit 308 is operable to deliver an output signal either by left shifting by one digit or without shifting an output value (on a data line L34) of the adder-subtracter circuit 307. Multiplexers 309 and 311 are each a 2-input 1-output selector. Responsive to sign values (Xs, Ys) of the two input operands and a subtraction execution signal sub, the shift signal generator circuit 310 delivers a signal purporting that execution operation is addition. An adder-subtracter circuit 312 responds to the signal delivered out of the shift signal generator circuit 310 to determine whether addition or subtraction is to be executed. If addition is to be executed, the circuit 312 executes in parallel addition of an exponent value delivered out of the multiplexer 311 and "0" and addition of the exponent value and "1" and thereafter responds to a signal (on L35) delivered out of the adder-subtracter circuit 307 so as to select one of the addition results.
The operation of the prior art shown in FIG. 3 will now be described. The two input operand exponent parts (Xe, Ye) are inputted to the subtracter circuit 303, non-normalized number detector circuit 301 and multiplexer 311. At the same time, the operand mantissa parts (1.Xf or 0.Xf; 1.Yf or 0.Yf) are inputted to the swap circuit 302. Firstly, the subtracter circuit 303 calculates a shift amount .vertline.Xe-Ye.vertline. of the operand mantissa parts which is necessary for making the exponent values equal and a sign S(Xe-Ye). When the two operands are of normalized numbers or of non-normalized numbers, the bias values in the exponent parts are the same for the two operands as shown in formula (1) (-127 for normalized number and -126 for non-normalized number) and therefore the shift amount applied to the right barrel shift circuit 305 is .vertline.Xe-Ye.vertline.. This shift amount is calculated in the subtracter circuit 303. However, when one of the two operands is of normalized number and the other is of non-normalized number, the bias values in the exponent parts are different by one for the normalized and non-normalized numbers as shown in formula (1) and therefore the shift amount of operand mantissa parts for making the exponent parts equal must be .vertline.Xe-Ye.vertline.-1. In other words, the output value of the subtracter circuit 303 has to be corrected. For example, given that the operand X is a normalized number and the operand Y is a non-normalized number, they are indicated by equation (2): EQU X=(-1).sup.Xs 1.Xf * 2.sup.Xe-127 EQU Y=(-1).sup.Ys 0.Yf * 2.sup.0-126 ( 2)
At that time, the shift amount of the mantissa part of the operand Y calculated by means of the subtracter 303 measures ".vertline.Xe-0.vertline.". However, the bias values of the exponent parts of the operands X and Y are "-127" and "-126" which differ from each other by one. Accordingly, even when the mantissa part "0.Yf" of operand Y is right shifted by ".vertline.Xe-0.vertline." to add ".vertline.Xe-0.vertline." to the exponent part "-126", equality of the exponent parts of the operands X and Y can not be obtained. In order to make equal the exponent parts of the operands X and Y, one must further be subtracted from the aforementioned right shift amount .vertline.Xe-0.vertline. and the mantissa part must be right shifted by the resulting value. The above description has been given by way of addition but the same is true for subtraction of the two operands. Thus, the subtracter circuit 304 corrects the shift amount of operand mantissa parts used to make equal the exponent values in executing the addition-subtraction of normalized and non-normalized numbers.
Concurrently with the execution of subtraction of the exponent parts by the subtracter circuit 303, the non-normalized number detector circuit 301 performs detection as to whether the operands X and Y are non-normalized numbers or not. When the exponent parts of the operands X and Y are zero, they are non-normalized numbers. If one of the two operands is of non-normalized number, the multiplexer 309 selects the output signal (.vertline.Xe-Ye.vertline.-1) from the subtracter circuit 304. If the operands are both normalized numbers or non-normalized numbers, the multiplexer 309 selects the output signal (.vertline.Xe-Ye.vertline.) from the subtracter circuit 303, thereby determining the shift amount to be inputted to the right barrel shift circuit 305.
The multiplexer 311 responds to the sign S(Xe-Ye) of the exponent subtraction value delivered out of the subtracter circuit 303 so as to select and deliver larger one of the Xe and Ye. The larger exponent value is a candidate for an exponent value as a result of the addition-subtraction.
The operand mantissa parts (1.Xf or 0.Xf; 1.Yf or 0.Yf) will now be described. In accordance with the sign S(Xe-Ye) calculated by the subtracter circuit 303, the swap circuit 302 performs swapping of the operand mantissa parts as will be described below. When Xe-Ye is positive or zero (S(Xe-Ye) &gt; or =0), the X operand mantissa parts (1.Xf or 0.Xf) is delivered to the data line L31 with the Y operand mantissa parts (1.Yf or 0.Yf) delivered to the data line L32. When negative (S(Xe-Ye) &lt;0), the input values are swapped and delivered. Then, an output signal delivered from the swap circuit 302 to the data lien L31 is applied directly to the right shift circuit 306 and an output signal delivered to the data line L32 is applied directly to the right barrel shift circuit 305.
In the above operation, problems are encountered. A delay in data transmission will be considered between the timing for inputting the two operands and the phase of processing in the right barrel shift circuit 305. The longest path having relation to the operand mantissa parts (1.Xf or 0.Xf; 1.Yf or 0.Yf) reacting the right barrel shift circuit 305 is a path in which the sign (S(Xe-Ye)) of difference between the exponent values is determined by the subtracter circuit 303 to control the swap circuit 302 such that an operand mantissa part data piece associated with smaller one of the exponent values is inputted to the right barrel shift circuit 305.
Further, the longest path having relation to data of the shift amount reaching the right barrel shift circuit 305 is a path in which .vertline.Xe-Ye.vertline.-1 is calculated using the subtracter circuits 303 and 304 and this value is inputted to the right barrel shift circuit 305 through the multiplexer 309. Obviously, the number of delay stages is larger in the latter path for calculation of the shift amount than in the former path because the data passes through the two subtracter circuits in the latter path. Thus, in the prior art floating point addition-subtraction apparatus, the two subtracter circuits are used to calculate the shift amount for digit matching and therefore the operation time is increased, with the result that the overall circuit of the apparatus is complicated and increased in size. With the circuit scale increased, power consumption increases disadvantageously.
The operational description of the prior art will now continue. The right shift circuit 306 responds to the shift signal (indicative of addition) from the shift signal generator circuit 310 to shift data on the data lines L31 and L33 by one digit to the right. The data on the data lines L31 and L33 suffer from a round-off position shift after execution of addition or subtraction of the data by means of the adder-subtracter circuit 307, and the right shift circuit 306 serves as a circuit for correcting the round-off position shift. The operation of the right shift circuit 306 will be described below.
During execution of addition and subtraction, there exist three patterns in total: EQU normalized number.+-.normalized number (3-1) EQU normalized number.+-.non-normalized number (3-2) EQU non-normalized number.+-.non-normalized number (3-3).
The execution of the above three patterns without the use of the right shift circuit 306 will be described below.
When addition is executed in patterns (3-1), (3-2) and (3-3), the results before subjected to the round off processing by the adder-subtracter circuit 307 are as follows. In the case of pattern (3-1) or (3-2), the results before the round off processing take the state as indicated by (4-1) in which the uppermost "1" of the mantissa part is at the second upper digit above the point or the state as indicated by (4-2) in which the uppermost "1" of the mantissa part is at the first upper digit above the point. In the case of pattern (3-3), the results before the round off processing take the state as indicated by (4-3) or the state as indicated by (4-4). EQU 1 *.**** - - - ** .times.2.sup.Xe-127 ( 4-1) EQU 1.**** - - - ** .times.2.sup.Xe-127 ( 4-2) EQU 1.**** - - - ** .times.2.sup.0-126 ( 4-3) EQU 0.**** - - - ** .times.2.sup.0-126 ( 4-4)
When subtraction is executed in patterns (3-1), (3-2) and (3-3), the results before subjected to the round off processing are as follows. In the case of pattern (3-1) or (3-2), three kinds of results are obtained which are represented by the state having "1" at the first upper digit above the point as indicated by (5-1), the state having "1" at the first lower digit below the point as indicated by (5-2) and the state having "1" initially at the second or more lower digit below the point. In the case of (3-3), the results are always of non-normalized number as indicated by (5-4). EQU 1.**** - - - ** .times.2.sup.Xe-127 ( 5-1) EQU 0.1*** - - - ** .times.2.sup.Xe-127 ( 5-2) EQU 0.0*** - - - ** .times.2.sup.Xe-127 ( 5-3) EQU 0.**** - - - ** .times.2.sup.0-126 ( 5-4)
As will be understood from the foregoing one digit shift of the position of the uppermost numerical value "1" occurs between addition and subtraction when the results of addition and subtraction are of normalized number. This signifies that in rounding the results into a significant digit number, the position of round off of the addition results differs from the position of round off of the subtraction results. Thus, separate round off processing circuits have to be provided for addition and subtraction, resulting in an increase in the amount of hardware. Therefore, it is obviously profitable that the round off carry positions in addition and subtraction are made to be coincident with each other to permit the use of only one round off circuit. To this end one of the addition result and subtraction result is required to be digit matched to the other. In the prior art, the shift signal generator circuit 310 decides the kind of operation and in the case of addition, the right shift circuit 306 shifts the input operand by one bit to the right so that the round off position of the addition results may be coincident or aligned with the round off position of the subtraction results. In this way the addition results before round off processing can be changed from formula (4) to formula (6) to ensure that before the round off processing, the round off position of the addition results can be coincident with the round off position of the subtraction results. EQU 1.**** - - - ** .times.2.sup.Xe-127+1 ( 6-1) EQU 0.1*** - - - ** .times.2.sup.Xe-127+1 ( 6-2) EQU 0.1*** - - - ** .times.2.sup.0-126+1 ( 6-3) EQU 0.0*** - - - ** .times.2.sup.0-126+1 ( 6-4)
At that time, the addition operand is right shifted and consequently the exponent value is apparently increased by "+1". The increase in exponent value is corrected as will be described later. In this manner, the right shift circuit 306 shifts the input operand by one digit to the right in the case of addition to fill the role of making the round off position coincident with that in the case of subtraction.
Data delivered out of the right shift circuit 306 is applied to the adder-subtracter circuit 307 where it is subjected to addition-subtraction and subsequent rounding, and the results are delivered to the data line L34. Delivered to the data line L35 is a value at the first upper digit above the point of the addition-subtraction results.
Thereafter, the left shift circuit 308 and the adder-subtracter circuit 312 are used to execute the normalization processing. During the normalization processing, the correction of the exponent value obtained in the case of addition is executed.
Delivered to the data line L34 are operation results as indicated in the mantissa parts in formulas (5) and (6). Strictly, formula (5) and (6) show values obtained before the mantissa part is subjected to rounding but since any of the data formats indicated in these equations will be conserved after the round off processing, those values will be used. The normalization processing will now be described in connection with addition and subtraction.
In the case of addition, when "1" is at the first upper digit above the point (data line L35=1) as indicated by (6-1), the left shift circuit 308 delivers data (mantissa value) on data line L34 as it is. As regards the exponent value, on the other hand, the adder-subtracter circuit 312 executes Xe+1 and delivers it. This ensures that the bias value of exponent value can be "-127" and the mantissa value can be delivered in a format of normalized number of "1. ***". Then, when "0" is at the first upper digit above the point (data line L35=0) as indicated by (6-2), (6-3) and (6-4), the left shift circuit 308 delivers an output signal by shifting data (mantissa value) on data line L34 by one digit to the left. As regards the exponent value, on the other hand, the adder-subtracter circuit 312 executes Xe+0 and delivers it. In this manner, the normalization processing is executed for (6-2), and data of (6-4) is permitted to be delivered in the form of a non-normalized number. Data for (6-3) is subjected to normalization during the subsequent cycle by using different hardware.
In the case of subtraction, when "1" is at the first upper digit above the point (data line L35=1) as indicated by (5-1), the left shift circuit 308 delivers an output signal without shifting data (mantissa value) on data line L34. On the other hand, the adder-subtracter circuit 312 executes subtraction Xe-0 and delivers it as an exponent value, thereby realizing the normalization processing. When "0" is at the first upper digit above the point (data line L35=0) as indicated by (5-2), (5-3) and (5-4), the left shift circuit 308 shifts data (mantissa value) on data line L34 by one digit to the left. On the other hand, the adder-subtracter circuit 312 executes subtraction Xe-1. In this manner, the normalization processing is executed for (5-2). Data for (5-3) or data for (5-4) is subjected to normalization or non-normalization during the subsequent cycle by using different hardware.
As is clear from the foregoing, the right shift circuit 306 needed for coincidence of the round off positions in addition and subtraction is inserted in a critical path as viewed from the whole floating point addition-subtraction apparatus. In other words, disadvantageously, the provision of the right shift circuit 306 further retards the operation speeds of the floating point adder-subtracter.